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NJW1262 -1- NJW1262ver.4.0_e analog signal input class-d amplifier for piezo speaker with dc-dc converter q general description q package outline the NJW1262 is an analog signal input monaural class-d amplifier for piezo speaker. and a built-in dc-d c converter generates fixed output voltage. therefore, it realizes 7v rms@1khz output signal with louder sound and high efficiency. the NJW1262 incorporates btl amplifier, which eliminate ac coupling capacitors, and it is capable of driving piezo speaker with simple external lc low-pass filters. class-d operation achieves lower power operation for piezo speaker, thus the NJW1262 is suited fo r battery-powered applications. q features o output voltage vdd=3.0v to 4.2v vddo=13.0v@sp mode vddo=4.5v@rec mode o analog audio signal input o 2input selector (speaker mode and receiver mode) o 1-channel btl output, piezo speaker driving o built-in dc-dc converter o built-in low voltage detector o standby (hi-z), soft start, soft mute control o built-in pop noise reduction o built-in short protector) o built-in thermal protection o package outline: epcsp32 q block diagram NJW1262nl2 eq 1 eq 2 bias r osc1 v dd v ddo out p out n v ssreg v ss in sp pulse width mo d u l a to r ocp v dd uvlo sw v ddo uvlo level shifter level shifter ocp tsd com com stbyb in prec mo d e out test control logic pulse width mod ul ator osc in- fb in nrec selector eq 3 soft - r osc2
NJW1262 - 2 - NJW1262ver.4.0_e q pin configuration no. symbol i/o function 23 v dd power supply:v dd =3.7 v 28,29 v ddo output power supply:v ddo =13 v 11 in sp i n oninverted signal input (sp mode) terminal 7 in prec i n oninverted signal input (rec mode) terminal 6 in nrec i inversion signal input (rec mode) 12 eq 1 i/o lpf setting terminal 13 eq 2 i/o lpf setting terminal 14 eq 3 i/o lpf setting terminal 5 com i/o bias terminal 19 soft i/o capacitor connection terminal for soft start 4 stbyb i standby control terminal (stbyb =l: standby) 3 mode i sp/rec mode switch terminal (mode =h: sp mode, mode =l: rec mode) the mode maintains the logic when the stbyb terminal is started up. 22 r osc1 i/o class-d amplifier oscillator resistance connection terminal 10 r osc2 i/o switching regulator oscillator resistance connection terminal 26,31 v ss gnd:v ss =0 v 30 out p o n oninverted signal output terminal 27 out n o inversion signal output terminal 2 out test o te s t p i n ( 5 0 k ? ground) should be floating or v ss fixation. 18 sw o inductor connection terminal 15 v ssreg gnd:v ssreg =0 v 21 in- i/o phase compensating device connection terminal for switching regulator 20 fb i/o phase compensating device connection terminal for switching regulator 8 test1 i te s t p i n ( 5 0 k ? ground) should be floating or v ss fixation. 1, 9,16,17, 24,25,32 nc nc pin should be floating or v ss fixation. note: v bat = v dd note: do not do floating the input terminal. q terminal configuration 1 8 916 24 17 32 25 out n nc nc nc nc nc test1 out p v ddo v ddo v ss v ss mod e stbyb out test v ssreg sw v dd fb in- r osc1 com in prec in nrec soft nc nc in sp eq 1 eq 2 eq 3 r osc2
nju3555 nju3555 NJW1262 -3- NJW1262 ver.4.0_e input terminal vss te r m i n a l internal circuit
NJW1262 - 4 - NJW1262ver.4.0_e q absolute maximum ratings (ta=25 c) parameter symbol conditions rating unit supply voltage v dd v ddo v dd v ddo -0.3 to +5.5 -0.3 to +36 v input voltage v in in sp , in prec , in nrec , stbyb, mode, out test -0.3 to v dd +0.3 v operating temperature topr -40 to +85 c storage temperature tstg -40 to +125 c p dmax2 2 layers (eiaj), t j = 125 c 760 mw power dissipation p dmax4 4 layers (eiaj), t j = 125 c 1800 mw ja2 2 layers (eiaj), t j = 125 c 132 c /w thermal resistance ja4 4 layers (eiaj), t j = 125 c 54 c /w note 1) all voltage are relative to ?v ss =0v? reference. note 2) power dissipation is a value in condition where it is mounted on 2-layer/ 4-layer board based on eia/jedec. note 3) the ic must be used inside of the ?absolute maximum ratings?. ot herwise, a stress may cause permanent damage to the lsi. note 4) de-coupling capacitors must be connected between each power supply terminal and gnd (v dd -v ss , v ddo -v ss ). note 5) the maximum power dissipation in the system is calculated, as shown below. [] [] [] w / c c t c t p ja a jmax dmax ? = pdmax: maximum power dissipation, tjmax: junction temperature = 125 c ta: ambient temperature, ja: thermal resistance of package = 132 c/w [] mw 570 w / 132 50 125 p d = ? = ? ? ?
nju3555 nju3555 NJW1262 -5- NJW1262 ver.4.0_e q electrical characteristics o dc characteristics t a = 25 c,v dd = 3.7 v, v ddo = 13.0 v(sp mode), v ddo = 4.5v (rec mode), v ss = v ssreg = 0.0 v, load= 1.5 f, r osc1 = 82 k ? , r osc2 = 82 k ? , c lpf = 330 pf, cc=0.033 f, output filter: [l out = 22 h, r damp = 3.9 ? ] sw regulator: [l sw = 6.8 h, c sw = 20 f+ 0.1 f, c cmpn1 = 4.7 nf, r cmpn = 68 k ? ] input signal :in sp = 100 mvrms, in prec - in nrec =100 mvrms, input frequency= 1 khz parameter symbol conditions min. typ. max. unit supply voltage v dd 3.0 3.7 4.2 v v swsp sp mode 11.9 13 14.1 v boost voltage v swrec rec mode 4.2 4.5 4.8 v r onhsp sp mode, out p , out n v outp, n = v ddo - 0.1 v 1.3 2.0 2.4 ? output driver on-state resistance (high-side) r onhrec rec mode, out p , out n v outp, n = v dd - 0.1 v 1.3 2.2 2.8 ? r onlsp sp mode, out p , out n v outp, n = 0.1 v 1.3 2.0 2.4 ? output driver on-state resistance (low-side) r onlrec rec mode, out p , out n v outp, n =0.1 v 1.3 2.2 2.8 ? switching regulator output driver on-state resistance r onsw sw v sw = 0.1 v 0.05 0.4 0.7 ? r insp in sp 90 120 150 k ? r inprec in prec 180 240 300 k ? input impedance r innrec in nrec 280 360 440 k ? operating current (standby) i st stbyb: "l",no load - - 1 a i batsp sp mode, non-lc filter, no load - 11 14 ma operating current (no signal input) i batrec rec mode non-lc filter, no load - 4.0 5.0 ma
NJW1262 - 6 - NJW1262ver.4.0_e parameter symbol conditions min. typ. max. unit v ih stbyb, mode pin 1.5 - v dd v input voltage v il stbyb, mode pin 0 - 0.5 v input leakage current i lk stbyb, mode pin - - 1 a sw off leak current i lksw sw pin - - 1 a out p ground resistance r outp out p pin 70 100 130 k ? out n ground resistance r outn out n pin 70 100 130 k ? class-d amplifier oscillation frequency f oscd 180 250 320 khz switching regulator oscillation frequency f oscsw 500 600 750 khz soft start resistance r sst soft pin 35 50 65 k ? soft mute resistance r smt soft pin 35 50 65 k ? start-up time t on 5.0 6.7 8.4 ms stop time t off 10 13.3 16.6 ms av sp sp mode, no load c lpf =100 pf - 27.6 - db class-d amplifier voltage gain av rec rec mode, no load c lpf =100 pf - 5.1 - db mode setup time t stup refer to figure 1. 10 - - s mode holding time t hld refer to figure 1. 50 - - s offset voltage v offset rec mode 2ms after out p and out n pin start switching -20 - 20 mv figure 1: stbyb/mode input timing stbyb mo d e t stup t hld
nju3555 nju3555 NJW1262 -7- NJW1262 ver.4.0_e o ac characteristics t a = 25 c,v dd = 3.7 v, v ddo = 13.0 v(sp mode), v ddo = 4.5v (rec mode), v ss = v ssreg = 0.0 v, load = 1.5 f, r osc1 = 82 k ? , r osc2 = 82 k ? , c lpf = 330 pf, cc=0.033 f, output filter: [l out = 22 h, r damp = 3.9 ? ] sw regulator: [l sw = 6.8 h, c sw = 20 f+ 0.1 f, c cmpn1 = 4.7 nf, r cmpn = 68 k ? ] input signal :in sp = 100 mvrms, in prec - in nrec =100 mvrms, input frequency= 1 khz parameter symbol conditions min. typ. max. unit thd+n sp sp mode, v outsp =2.5 vrms - 0.2 - % thd+n thd+n rec rec mode v outrec =1 vrms - 0.08 - % v outsp sp mode, thd+n=2 % - 7 - v rms maximum output voltage v outrec rec mode, thd+n=2 % - 2.7 - vrms s/n sn rec mode, v outrec =1 vrms a-weight - 80 - db noise floor v n rec mode, a-weight - 100 - vrms note) a noise by the class-d amplifier oscillation frequ ency and the switching regulator oscillation frequency may be felt in receiver mode. therefore, please test the circuit carefully to fit your application.
NJW1262 - 8 - NJW1262ver.4.0_e q functional description o signal input terminal (in sp, in prec, in nrec ) analog signal input. the input signal is selected by the operational mode. o capacitor connection terminal for lpf (eq1, eq2, eq3) the amount of current passing through a capacitive load increases proportionately with frequency of audio signal. input filters should be put in the input line to reduce load current at high frequency-band. the input low pass filters are composed of feedback resister (r 1 ) and capacitor (c lpf ). refer to the following expression. r 1 = 120k ? , c lpf = 330pf [khz] 0 . 4 pf 330 k 120 3.14 2 1 c r 2 1 f lpf 1 lpf ? = = figure 2: input lpf composition o signal output terminal (out p , out n ) the output signals are pwm signals, whic h will be converted to analog signal via external 2nd-order or higher lc filter. should be connected to the damping resistor (r damp ) between out p pin and coil, and between out n pin and coil to reduce the current consumption with si gnal-input close to cutoff-frequency of lpf (f c ). set the value of lout, cl, and rdamp to become q<1. refer to the following expression. l out =22 h, c l =1.5 f, r damp =3.9 ? , equivalent series resistance of l (r dcr ) =0.8 ? [khz] 6 . 19 f 5 . 1 h 22 2 3.14 2 1 c l 2 2 1 f l out c = = 63 . 0 f 5 . 1 2 h 22 4 . 0 9 . 3 1 c 2 l r r 1 q l out dcr damp ? + ? = + = r 1 =120[k ? ]
nju3555 nju3555 NJW1262 -9- NJW1262 ver.4.0_e o standby terminal (stbyb) by setting the stbyb pin to ?l? level, it switches the NJW1262 into standby cond ition. during the standby condition, output pins (out p , out n , sw) become high impedance and class-d amplifier output is connected with v ss with about 100k ? . keep the stbyb pin to ?l? level at least 13.3ms once switched into the standby condition. for normal operation, the stbyb pin requires ?h? leve l. time from the standby release to class-d power amplifier operation is 6.7ms(typ). do not change to the standby mode until the power amplifier operation. set the standby mode at power supply on/off. o capacitor connection terminal for soft start (soft) capacitor connection terminal for soft start and soft mute. o step-up switching regulator the switching regulator is used as power supply (v ddo ) for power amplifier of class-d. the pwm controlled switching regulator works with external components, which are coil, capacitor, schottky barrier diode. r sft =50[k ? ] c sft =0.1[ f] v ss v dd soft c sft r sft r sft 40'545"35 $*3$6*5
NJW1262 - 10 - NJW1262ver.4.0_e o mode sp/rec mode selection terminal. the output power-sup ply voltage, the input selector, and the voltage gain change when the mode is switched. mode= l h z :sp speaker mode audio input terminal: in sp (shingle end input) class-d amplifier output power-supply voltage: step-up switching regulator ) ( 0 . 13 1 0 . 1 2 1 typ v r r v v sp swsp = ? ? ? ? ? ? ? ? + = voltage gain: 27.6 db (typ) mode= l l z rec receiver mode audio input terminal: in prec z in nrec (difference input) class-d amplifier output power-supply voltage: step-up switching regulator ) ( 5 . 4 1 0 . 1 2 1 typ v r r v v rec swrec = ? ? ? ? ? ? ? ? + = voltage gain: 5.1 db (typ) switching regulator circuit note) reset it when you switch mode. (stbyb?l") o low voltage detector when the power-supply voltage drops down to below v dd , the output driver is turned off output pins (out p , out n , sw) become high impedance and class-d amplifier output is connected with v ss with about 100k ? .
nju3555 nju3555 NJW1262 -11- NJW1262 ver.4.0_e o short circuit protection the short-circuit protection circuit opera tes at the condition of the following. -short between out p and out n - power supply short and earth fault of out p terminal - power supply short and earth fault of out n terminal - power supply short of sw terminal when out p and out n of the short-circuit protec tion circuit operates, the out p and out n become high impedance and class-d amplifier output is connected with v ss with about 100k ? . it restarts by pulse-by-pulse of built-in clock of class-d amplifier. when sw terminal of the short-circ uit protection circuit operates, the sw terminal become high impedance. it restarts by pulse-by-pulse of built-in clock of the switching regulator . note) *1 the detectable current and the peri od for the protection depend on the power supply voltage, chip temperature and ambient temperature. *2 the short protector is not effective for a long term short-circuit current but for an instantaneous accident. continuous high current may cause permanent damage to the NJW1262. o thermal protection when the junction temperature is more than specified val ue, the output driver is turned off output pins (out p , out n , sw) become high impedance and class-d amplifier output is connected with v ss with about 100k ? . when the junction temperature is less than specified value, protection is released. o out test pin this pin is jrc?s test pin. q total harmonic distortion measurement circuit
NJW1262 - 12 - NJW1262ver.4.0_e q typical application circuit note) de-coupling capacitors must be connected between each power supply terminal and gnd (v dd -v ss , v ddo -v ss ). note) c dd2 (v dd -v ss ) should be connected at a nearest point to the ic on pcb. note) v ss and v should be connected at a nearest point to the ic on pcb. note) in sp , in prec , in nrec , eq 1 , eq 2 and eq 3 should be not designed near out p, out n and sw, which emit pwm noise. note) the transition time for mode and stbyb signals must be less than 100 s. otherwise, a malfunction may be occurred. note) the above circuit shows only application ex ample and does not guarantee the any electrical characteristics. therefore, pl ease test the circuit carefully to fit your application. note) the speaker should be designed at a near the ic. [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. q recommended parts cl: vslbp2115e1100-t1(murata) csw1: grm31cb31e106ka75l (murata) 2 cdd1: grm31cb31e106ka75l(murata) cdd2,csw2, csft: grm155b31e104ka87d(murata) ccsp, ccprec, ccnrec: grm 033b10j333ke01d (murata) clpf1, clpf2: grm155b 11h331ka01d(murata) ccm: grm155b31a105ke15d(murata) lsw: lqh44pn6r8mpo(murata) lout: lqh44pn220mp0(murata) dsw: rsx201va-30(rohm) rdamp: erj-14yj3r9u(panasonic) q specifiedparts rosc1, rosc2 = rk73h1jttd8202f(koa)
nju3555 nju3555 NJW1262 -13- NJW1262 ver.4.0_e q package information
NJW1262 - 14 - NJW1262ver.4.0_e [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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